AD9846AJST |
RFQ for AD9846AJST Required Field |
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| Technical/Catalog Information | AD9846AJST |
| Vendor | Analog Devices Inc |
| Category | Integrated Circuits (ICs) |
| Package / Case | 48-LQFP |
| Packaging | Tray |
| Type | CCD Signal Processor |
| Interface | Microprocessor |
| Supply Voltage | 4.75 V ~ 5.25 V |
| Current - Supply | 86mA |
| Input Type | Logic |
| Output Type | Logic |
| RoHS Status | RoHS Non-Compliant |
| Other Names | AD9846AJST AD9846AJST |
| Product | Manufacturers | Pack | D/C |
| AD9846AJST | - | QFP-48 | - |
The AD9846A is a complete analog signal processor for CCD applications. It features a 30 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9846A's signal chain consists of an input clamp, correlated double sampler (CDS),Pixel Gain Amplifier (PxGA), digitally controlled variable gain amplifier (VGA), black level clamp, and a 10-bit A/D con-
verter. Additional input modes are provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power-down modes.The AD9846A operates from a single 3 V power supply, typi- cally dissipates 117 mW, and is packaged in a 48-lead LQFP.
The AD9846A operates from a single 3 V power supply, typically dissipates 117 mW, and is packaged in a 48-lead LQFP.
Typical Application |
Features |
| The AD9846A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 32, the CCD image (pixel) data is buffered and sent to the AD9846A analog input through a series input capacitor. TheAD9846A performs the dc restoration, CDS, gain adjustment,black level correction, and analog-to-digital conversion. The AD9846A's digital output data is then pro cessed by the imageprocessing ASIC. The internal registers of the AD9846A-used to control gain, offset level, and other functions-are programmed by the ASIC or microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE. | 30 MSPS Correlated Double Sampler (CDS) 4 dB ±6 dB 6-Bit Pixel Gain Amplifier (PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 30 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 100 mW @ 2.7 V 48-Lead LQFP Package |
| Parameter | With Respect To | Min Max | Unit |
| AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL BYP1-4, CCDINJunction Temperature Lead Temperature (10 sec) |
AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS |
0.3+3.9 0.3+3.9 0.3+3.9 0.3DRVDD + 0.3 0.3DVDD + 0.3 0.3DVDD + 0.3 0.3DVDD + 0.3 0.3AVDD + 0.3 0.3AVDD + 0.3 150 300 |
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